|工作年限：||3 - 4年||学 历：||本科|
1.Follow working flow to implements IC design with emphasis on layout tasks, including floor plan, power planning, parasitic extraction, ESD, physical verification independently.
2.can modify DRC, LVS runset files is a plus
3.familiar use Encounter to APR is a plus
4.Generate and release tape-out kit.
5.documentations and delivery.
6.Training for new hires.
1.A BS/MS degree in electrical engineering or related discipline.More that 3 years experience in physical design.
2.Expertise in analog/Mixed signal, IO,STD,Memory layout of high-speed &high-precision design.
3.Excellent knowledge in ESD, ERC, DFM,IR drop, EM, and IC manufacturing process in deep sub-macro design.
4.Experience in Synopsys/cadence design tools and flows.
5.Experience in scripting languages(Perl,Tcl,Shell,...)is plus.
6.Experience in PR is preferred.
7.Open mind, self-motivated, excellent communication skills and ability to excel in a team environment.