|工作年限：||3 - 4年||学 历：||本科|
1.Responsible for Specification definition.
2.Developing complex digital designs with emphasis on Front-End, including Coding, Simulation, Constrain and Synthesis.
3.Responsible for developing high-speed digital designs with Schematic, including schematic, simulation and timing/power/performance optimization.
4.Transistor level design and Circuit layout supervision.
5.Test-bench and Test-pattern generation to full-cover the relative design.
The Successful candidate will have:
1.A MSEE with minimum of 3 years experience or a BSEE with a minimum of 5 years experience in digital circuit design.
2.Proven experience in complex digital control circuit design; Good Verilog RTL coding skills along with good debugging skills.
3.Good knowledge of test benches, synthesis,timing analysis and DFT is preferred.
4.Good knowledge of FPGA verification is a plus.
5.Good communication skills and High grade of flexibility.
6.Highly motivated and engaged.
7.Experience in Flash/SRAM and DRAM design is preferred.